Integrated circuit devices, commonly known as chips, continue to become more powerful and complex as semiconductor manufacturing technologies have advanced. Whereas early integrated circuit devices included fewer than one hundred transistors, it is now common to integrate millions of transistors into a single integrated circuit device. This increased transistor count enables some operations that once required several integrated circuit devices to now be implemented in a single integrated circuit device, often providing greater performance at a lower cost. For example, where previously a data processing system might require separate integrated circuit devices for a microprocessor, a memory, a bus interface, and a memory controller, advances in chip density now permit all of these functions to be integrated into the same integrated circuit device. Such devices are typically known as “systems on a chip” due to the high level of integration they provide.
Increases in chip density have also significantly affected the design methodologies used for integrated circuit chips. Rather than manually laying out individual transistors or logic gates in a design to obtain a desired logic function, typically the functional aspects of the design process are separated from the physical aspects. The functional aspects of a design are typically addressed via a process known as a logic design, which results in the generation of a functional definition of a circuit design, typically defined in a hardware description language (HDL) such as VHDL or Verilog. An HDL representation of a circuit is analogous in many respects to a software program, as the HDL representation generally defines the logic or functions to be performed by a circuit design. Moreover, by separating logic design from physical layout, functions are capable of being defined at a higher level of abstraction.
In parallel with the creation of the HDL representation, a physical definition of a circuit design is created typically via a layout process, often referred to as integration, to essentially create a “floor plan” of logic gates and interconnects between the logic gates representing the actual physical arrangement of circuit elements on the manufactured integrated circuit. Automation tools have been developed to utilize predefined cells or blocks of complete circuits to assist with the layout, thus eliminating the need to work with millions of individual logic gates. For example, synthesis tools have been developed to generate Random Logic Macro (RLM) blocks from an HDL representation of a design, whereby an individual laying out a design is merely required to place the RLM blocks and connect them to one another to complete the circuit design. In addition, some designs incorporate blocks from off-the-shelf (OTS) logic blocks, which are reusable from design to design.
Once a physical definition is created, testing and simulation of the design may be performed to identify any potential timing and/or manufacturability issues, and once the design has been determined to meet these requirements, the design may be utilized to manufacture integrated circuits.
As integrated circuits have become more complex, the number of individuals involved in the development and testing processes has increased substantially. Indeed, in many instances the individuals performing the logic design process are completely separate from the integrators who perform the physical design processes. Furthermore, as integrated circuits have become more complex, larger and faster, timing issues become more pronounced, often necessitating the functional definition of a design to be revised after layout has been performed. In many instances, several iterations of reworking a functional definition, updating the physical definition, and retesting the physical definition may be required before timing issues are adequately resolved. With different individuals participating in these different processes, therefore, coordinating the updates to the functional and physical definitions can become problematic and time consuming.
One particular area, for example, where the layout process may require revision of a functional definition is associated with what is referred to herein as overhead logic, i.e., supplemental support circuitry that is not directly involved in the primary logic implemented by a circuit design. For example, in order to provide testability for a manufactured device, most integrated circuit designs include a scan architecture integrated therein with one or more serial chains of latches referred to as scan chains. The latches in a serial chain, or scan path, are designed such that, when configured in a specific mode, the latches together operate as a shift register so that data may be shifted into the chain of latches from a single source to simulate different conditions, and so that data generated within a device may be shifted out through a single output. Thus, with a scan architecture, the current state of various nodes in a device at any given time may be controlled and/or recorded and later accessed via external equipment to verify the operation of a manufactured device.
The latches in a scan chain are coupled together serially, typically with each latch having a scan in port and a scan out port, with the scan in port of each latch being connected to the scan out port of its preceding latch. Whereas less complex circuit designs might include tens or hundreds of latches in a single scan chain, more complex designs, e.g., many SOC designs, may require thousands of latches in a scan architecture. Furthermore, to ensure that the amount of time required to load and unload data into and out of a scan architecture, multiple scan chains are typically used, requiring each latch to be assigned to a specific scan chain, in addition to being assigned to a specific location in the selected scan chain.
Scan architectures may require additional clock control signals to be distributed to the various latches to enable and otherwise configure scan chain operation. With more complex integrated circuit designs, the size and timing constraints imposed on the designs often necessitate the use of distribution trees to distribute clock control signals and other overhead or non-overhead global signals. In a distribution tree, signals are distributed via a tree of latches that repower the signals, shorten effective wire lengths, and reduce fanout issues, while ensuring that the signals arrive at all endpoints at the same time. As a result, similar to the assignment of latches to scan chains, latches are often required to be connected to appropriate signals output from a distribution tree.
As a general design rule, it is desirable to utilize multiple balanced scan chains to reduce the length of each scan chain and thus reduce the amount of time required to test a circuit. Furthermore, it is often desirable to minimize the wire lengths used to connect the latches in a scan chain together, which is typically accomplished by grouping latches that are physically located in close proximity to one another into the same scan chain.
It is often desirable to maintain the assignments of latches to scan chains and distribution trees in a functional definition of a circuit design. With layout performed after logic design, however, the optimal assignment of latches to scan chains, as well as the assignment of latches to signal distribution trees, cannot be ascertained until after the design has been laid out. Often, a logic designer is required to initially connect latches to scan chains and distribution trees manually and based upon little more than educated guessing. Often, as a result of layout and testing, the latch connections must be modified manually to reduce wire lengths and achieve timing requirements. Given the iterative nature of the design process, repeated manual modifications may be required. This, in turn, makes it difficult to freeze the functional definition because the functional definition is dependent on layout changes and visa versa.
With large device integration, maintaining proper assignments becomes significantly problematic. For example, when a register (i.e., a group of latches) is physically moved any significant distance during integration, it often must be connected to a different node of a distribution tree and must be placed into a new position of a (possibly different) scan ring. A typical IP block may have dozens of registers (and as a result, hundreds of latches), each requiring separate distribution tree and scan chain assignments to be made. Some design sizes may yield on the order of 150 different distribution tree signals to choose from depending on the physical location of a register, and may incorporate 25 or more separate scan rings. As a result, the management of assignments can be a significant endeavor.
Increasing device frequencies typically drive more placement instabilities into a design, forcing integrators to make frequent changes to a device's floor plan. Since the connections to the scan architecture are not really a part of the functional logic, these changes are usually made without regard for the consequences on the scan architecture. Thus, the management of scan architecture connections, as well as those to other overhead circuitry in a circuit design, continues to increase in difficulty.